1. Field
The present invention relates to an erase operation of a NAND flash memory.
2. Related Art
The memory cell array of a NAND flash memory comprises NAND blocks. The word lines in the NAND blocks are connected via the respective transfer transistor units provided for the corresponding NAND blocks to a control gate line common to all of the NAND blocks.
When data is erased, the control gate line applies not only zero or negative potential to the word lines in the selected NAND block to be erased but also an erase potential of about 20 V to the well, thereby drawing electrons from the floating gates of the memory cells in the selected NAND block into the well.
At this time, the transfer transistors in the transfer transistor units corresponding to the unselected NAND blocks not to be erased are caused to remain off. That is, at the time of erasing, the word lines in the unselected NAND blocks are floating.
Therefore, when an erase potential of about 20 V is applied to the well, the word lines in the unselected NAND blocks are raised to about 20 V by capacitive coupling, which prevents the data from being erased from the memory cells in the unselected NAND blocks.
After the erase operation is completed, the charge accumulated in the well is discharged (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. H10-214491 and Jpn. Pat. Appln. KOKAI Publication No. 2008-4236).
It is desirable that the period during which the charge in the well is discharged should be shorter. However, it cannot be made just shorter.
The reason is as follows. Although the word lines in the selected NAND block are held at zero potential, if the well discharges too quickly, there is a danger that the word lines in the selected NAND block will drop to a negative potential because of capacitive coupling when the discharge of the well begins.
If such a situation takes place, the control gate line will also drop to a negative potential. This causes the transfer transistors in the transfer transistor units corresponding to the unselected NAND blocks to be changed from off to on, with the result that the potential of the word lines in the unselected NAND blocks drops from about 20 V to zero.